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In computer architecture, a bus is a communication system that transfers data between
componentsinside acomputer, or between computers. This expression
covers all related hardware components (wire, optical fiber, etc.) and
software, including communication protocols.Early computer buses were
parallel electrical wires with multiple connections, but the term is
now used for any physical arrangement that provides the same logical
functionality as a parallelelectrical bus. Modern computer buses can
use bothparallelandbit serialconnections, and can be wired in either
amultidrop(electrical parallel) ordaisy chaintopology, or connected by
switched hubs, as in the case ofUSB.
Databusmay refer to: A data bus is a computer subsystem that allows
for the transferring of data from one component to another on a
motherboard or system board, or between two computers. This can
include transferring data to and from the memory, or from the central
processing unit (CPU) to other components. Each one is designed to
handle so many bits of data at a time. The amount of data a data bus
can handle is called bandwidth.
An address bus is a computer busarchitecture used to transfer data
between devices that are identified by the hardware address of the
physical memory (the physical address), which is stored in the form of
binary numbers to enable the data bus to access memory storage.The
address bus is used by the CPU or a direct memory access (DMA) enabled
device to locate the physical address to communicate read/write
commands. All address busses are read and written by the CPU or DMA in
the form of bits.
A control bus is a computer bus that is used by the CPU to communicate
with devices that are contained within the computer. This occurs
through physical connections such as cables or printed circuits.The
CPU transmits a variety of control signals to components and devices
to transmit control signals to the CPU using the control bus. One of
the main objectives of a bus is to minimizethe lines that are needed
for communication. An individual bus permits communication between
devices using one data channel. The control bus is bidirectional and
assists the CPU in synchronizing control signals to internal devices
and external components. It is comprised of interrupt lines, byte
enable lines,read/write signals and status lines.
Ans. Computer Architecture:
It is concerned with structure and behaviour of computer as seen by the user. It includes the information formats, the instruction set, and techniques for addressing memory of a computer system is concerned with the specifications of the various functional modules, such as processors and memories and structuring them together into a computer system.
Stored program concept:-
This as introduced in late 1940s by John Von Neumann,Who proposed that a program stored in a binary –number format in a memory device so that instruction could be modified by the computer as determined by intermediate computational result .
Ans. NAND logic and NOR logic gates are universal logic. It is possible to implement any logic expression by NAND and NOR gates. This is because NAND and NOR gates can be used to perform each of Boolean operations INVERT, AND and OR. NAND is same as AND gate symbol except that it has a small circle at output. This a small circle represents the universal operations.
Ans. Shift registers are the sequential logic circuit used to shift the data from registers in both directions. Shift registers are designed as a group of flip-flops connected together so that the output from one flip-flop becomes the input to the next flip-flop. The flip-flop are driven by a common clock signals and can be set or reset simultaneously. Shift registers can be connected to form different type of counters.
Gray coding is an important code and is known for its speed. This code is relatively free from the errors. In binary coding or 8421 BCD, counting from 7(0111) to 8(1 000) requires 4-bits to be changed simultaneously. Gray coding avoids this by following only one bit changes between subsequent numbers.
Ans. The concepts of layers in architectural design are described as below:
1. Complex problems can be segmented into smaller and more manageable form.
2. Each layer is specialized for specific functioning.
3. Upper layers can share the services of a lower layer. Thus layering allows us to reuse functionality.
4. Team development is possible because of logical segmentation.
A team of programmers will build. The system and work has to be sub-divided of along clear boundaries.
Ans. Computer Organisation: It is concerned with the way the hardware components operate and the way they are connected together to form the computer system. The various components are assumed to be in place and the task is to investigate the organisational structure to verify that the computer parts operate.
Ans. Computer Architecture : It is concerned with structure and behaviour of computer as seen by the user. It includes the information formats, the instruction set, and techniques for addressing memory of a computer system is concerned with the specifications of the various functional modules, such as processors and memories and structuring them together into a computer system.
The three different types of mapping used for the purpose of cache memory are as follow,
Associative mapping, Direct mapping and Set-Associative mapping.-
Associative mapping: In this type of mapping the associative memory is used to store content and addresses both of the memoryword. This enables the placement of the any word at any place in the cache memory. It is considered to be the fastest and the most flexible mapping form.-
Direct mapping: In direct mapping the RAM is made use of to store data and some is stored inthe cache. An address space is splitinto two parts index field and tag field. The cache is used to store the tag field whereas the rest is stored in the main memory. Directmapping`s performance is directly proportional to the Hit ratio.- Set-associative mapping: This form of mapping is a modified form of the direct mapping where the disadvantage of direct mappingis removed. Set-associative mapping allows that each word thatis present in the cache can have two or more words in the main memory for the same index address.
The three different types of mapping used for the purpose of cache memory are as follow,
Associative mapping,
Direct mapping and
Set-Associative mapping.-
1.Associative mapping: In this type of mapping the associative memory is used to store content and addresses both of the memoryword. This enables the placement of the any word at any place in the cache memory. It is considered to be the fastest and the most flexible mapping form.
Direct mapping:
IIn direct mapping the RAM is made use of to store data and some is stored inthe cache. An address space is splitinto two parts index field and tag field. The cache is used to store the tag field whereas the rest is stored in the main memory.
Direct mapping`s performance is© directly proportional to the Hit ratio.-
Set-associative mapping: This form of mapping is a modified form of the direct mapping where the disadvantage of direct mappingis removed. Set-associative mapping allows that each word thatis present in the cache can have two or more words in the main memory for the same index address.
No. | RISC | CISC |
| 1 | It is an acronym for Reduced Instruction Set Computer. It is a type of microprocessor that has been designed to carry out few instructions at the same time. | CISC stands for Complex Instruction Set Computer. It is actually a CPU which is capable of executing many operations through a single instruction. |
2 | Faster than CISC | Slower than RISC chips when performing instructions |
3 | Pipelining can be implemented easily | Pipelining implementation is not easy |
| 4 | Direct addition is not possible | Direct addition between data in two memory locations. Ex.8085 |
5 | Simple, single-cycle instructions that perform only basic Functions. Assembler instructions correspond to microcode instructions on CISC machine | |
| 6 | RISC architecture is not widely used | At least 75% of the processor use CISC architecture |
7 | RISC chips require fewer transistors and cheaper to produce. Finally, it's easier to write powerful optimized compilers | In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions. |
8 | RISC puts a greater burden on the software. Software developers need to write more lines for the same tasks | In CISC, software developers no need to write more lines for the same tasks |
9 | Mainly used for real time applications | Mainly used in normal PC's, Workstations and servers |
10 | Large number of registers, most of which can be used as general purpose registers | CISC processors cannot have a large number of registers |
11 | RISC processor has a number of hardwired instruction | CISC processor executes microcode instructions |
| 12 | Uses Direct execution control unit. | Uses microcode control unit. |
| 13 | Price: move complexity from hardware to software. | Price: move complexity from software to hardware. |
14 | Performance: make tradeoffs in favor of a lower CPI, at the Expense of increased code size. | Performance: make tradeoffs in favor of decreased code size, at The expense of a higher CPI. |
Difference Between RISC and CISC
No. | RISC | CISC |
| 1 | It is an acronym for Reduced Instruction Set Computer. It is a type of microprocessor that has been designed to carry out few instructions at the same time. | CISC stands for Complex Instruction Set Computer. It is actually a CPU which is capable of executing many operations through a single instruction. |
2 | Faster than CISC | Slower than RISC chips when performing instructions |
3 | Pipelining can be implemented easily | Pipelining implementation is not easy |
| 4 | Direct addition is not possible | Direct addition between data in two memory locations. Ex.8085 |
5 | Simple, single-cycle instructions that perform only basic Functions. Assembler instructions correspond to microcode instructions on CISC machine | A large and varied instruction set that includes simple, fast instructions for performing basic tasks, as well as |
6 | RISC architecture is not widely used | At least 75% of the processor use CISC architecture |
7 | RISC chips require fewer transistors and cheaper to produce. Finally, it's easier to write powerful optimized compilers | In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions. |
8 | RISC puts a greater burden on the software. Software developers need to write more lines for the same tasks | In CISC, software developers no need to write more lines for the same tasks |
| 9 | Mainly used for real time applications | Mainly used in normal PC's, Workstations and servers |
10 | Large number of registers, most of which can be used as general purpose registers | CISC processors cannot have a large number of registers |
11 | RISC processor has a number of hardwired instruction | CISC processor executes microcode instructions |
| 12 | Uses Direct execution control unit. | Uses microcode control unit. |
| 13 | Price: move complexity from hardware to software. | Price: move complexity from software to hardware. |
14 | Performance: make tradeoffs in favor of a lower CPI, at the Expense of increased code size. | Performance: make tradeoffs in favor of decreased code size, at The expense of a higher CPI. |
